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Burst Transfer with FIFO Recovery Enabled
Burst Transfer with FIFO Recovery Enabled
CorePCIF directly supports connection of external FIFOs. When FIFOs are connected to the core, special logic is
implemented inside the core to prevent data loss. As seen in Figure 6-10 on page 59 to Figure 6-12 on page 61 , the core
reads ahead of the transfer on the PCI bus during a burst transfer so it can maintain high throughput. This is illustrated
in Figure 6-5 on page 56 . The core actually transfers four words on the PCI bus but reads seven from the backend
interface. Without the optional FIFO recovery logic, these additional three words would be lost.
When the FIFO recovery mode is enabled, BAR i _ENABLE = 2. The core will store these three words internally and
transfer them at the start of the next read cycle from the same BAR. Figure 6-14 shows an initial burst read cycle,
followed by a second read cycle that initially transfers data stored from the first transfer.
cycle
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
clk
framen
cben[3:0]
6
0
6
0
ad[31:0]
ADDR
0
1
2
3
ADDR
4
5
6
7
par
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
0
7
0
rd_cyc
rd_stb_out
rd_stb_in
mem_add[7:0]
00
04 08 0C 10 14
18
00
04
08
0C
mem_data_in[31:0]
0
1
2
3
4
5
6
7
8
9
rd_sync
Figure 6-14 · FIFO Recovery Operation (RD_SYNC = 0)
During the first read cycle, as shown in Figure 6-14 , the core reads six words from the backend but only transfers four
words on the PCI bus. The remaining two words, four and five, are stored in the core. On the second PCI burst read
cycle, the core reads the next data words, six and seven, from the backend before it stops to prevent its internal storage
from overflowing. At cycle five in the second PCI cycle, word four is transferred on the PCI bus. When the second PCI
cycle terminates, words eight and nine are left stored in the core.
When RD_SYNC = 1, a very similar pair of transfers occurs, but in this case, the first transfer actually reads seven words
and transfers four words on the bus, leaving three words stored in the core between the transfers.
v4.0
63
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